At TSMC’s North American Technology Symposium on Wednesday, the corporate detailed each its semiconductor know-how and chip-packaging know-how highway maps. Whereas the previous is essential to retaining the standard a part of Moore’s Regulation going, the latter might speed up a development towards processors created from increasingly silicon, main rapidly to methods the scale of a full silicon wafer. Such a system, Tesla’s next generation Dojo training tile is already in manufacturing, TSMC says. And in 2027 the foundry plans to supply know-how for extra advanced wafer-scale methods than Tesla’s that might ship 40 occasions as a lot computing energy as at this time’s methods.
For many years chipmakers elevated the density of logic on processors largely by scaling down the realm that transistors take up and the scale of interconnects. However that scheme has been operating out of steam for some time now. As a substitute, the trade is popping to superior packaging know-how that enables a single processor to be created from a bigger quantity of silicon. The dimensions of a single chip is hemmed in by the biggest sample that lithography gear could make. Referred to as the reticle restrict, that’s at the moment about 800 sq. millimeters. So if you would like extra silicon in your GPU it’s essential make it from two or extra dies. The bottom line is connecting these dies in order that indicators can go from one to the opposite as rapidly and with as little power as in the event that they had been all one huge piece of silicon.
TSMC already makes a wafer-size AI accelerator for Cerebras, however that association seems to be distinctive and is completely different from what TSMC is now providing with what it calls System-on-Wafer.
In 2027, you’re going to get a full-wafer integration that delivers 40 occasions as a lot compute energy, greater than 40 reticles’ value of silicon, and room for greater than 60 high-bandwidth reminiscence chips, TSMC predicts
For Cerebras, TSMC makes a wafer filled with similar arrays of AI cores which are smaller than the reticle restrict. It connects these arrays throughout the “scribe traces,” the areas between dies which are normally left clean, so the wafer will be diced up into chips. No chipmaking course of is ideal, so there are all the time flawed components on each wafer. However Cerebras designed in sufficient redundancy that it doesn’t matter to the completed pc.
Nevertheless, with its first spherical of System-on-Wafer, TSMC is providing a distinct resolution to the issues of each reticle restrict and yield. It begins with already examined logic dies to reduce defects. (Tesla’s Dojo accommodates a 5-by-5 grid of pretested processors.) These are positioned on a provider wafer, and the clean spots between the dies are stuffed in. Then a layer of high-density interconnects is constructed to attach the logic utilizing TSMC’s integrated fan-out technology. The intention is to make information bandwidth among the many dies so excessive that they successfully act like a single massive chip.
By 2027, TSMC plans to supply wafer-scale integration based mostly on its extra superior packaging know-how, chip-on-wafer-on-substrate (CoWoS). In that know-how, pretested logic and, importantly, high-bandwidth reminiscence, is hooked up to a silicon substrate that’s been patterned with high-density interconnects and shot by with vertical connections referred to as through-silicon vias. The hooked up logic chips may also make the most of the corporate’s 3D-chip technology referred to as system-on-integrated chips (SoIC).
The wafer-scale model of CoWoS is the logical endpoint of an enlargement of the packaging know-how that’s already seen in top-end GPUs. Nvidia’s next GPU, Blackwell, makes use of CoWos to combine greater than 3 reticle sizes’ value of silicon, together with 8 high-bandwidth reminiscence (HBM) chips. By 2026, the corporate plans to increase that to five.5 reticles, together with 12 HBMs. TSMC says that might translate to greater than 3.5 occasions as a lot compute energy as its 2023 tech permits. However in 2027, you will get a full wafer integration that delivers 40 occasions as a lot compute, greater than 40 reticles’ value of silicon and room for greater than 60 HBMs, TSMC predicts.
What Wafer Scale Is Good For
The 2027 model of system-on-wafer considerably resembles know-how referred to as Silicon-Interconnect Fabric, or Si-IF, developed at UCLA greater than 5 years in the past. The staff behind SiIF contains electrical and computer-engineering professor Puneet Gupta and IEEE Fellow Subramanian Iyer, who’s now charged with implementing the packaging portion of the United States’ CHIPS Act.
Since then, they’ve been working to make the interconnects on the wafer extra dense and so as to add different options to the know-how. “If you would like this as a full know-how infrastructure, it must do many different issues past simply offering fine-pitch connectivity,” says Gupta, additionally an IEEE Fellow. “One of many largest ache factors for these massive methods goes to be delivering energy.” So the UCLA staff is engaged on methods so as to add good-quality capacitors and inductors to the silicon substrate and integrating gallium nitride energy transistors.
AI coaching is the obvious first application for wafer-scale know-how, however it’s not the one one, and it might not even be the perfect, says College of Illinois Urbana-Champaign pc architect and IEEE Fellow Rakesh Kumar. On the International Symposium on Computer Architecture in June, his staff is presenting a design for a wafer-scale network switch for information facilities. Such a system might lower the variety of superior community switches in a really massive—16,000-rack—information heart from 4,608 to simply 48, the researchers report. A a lot smaller, enterprise-scale, information heart for say 8,000 servers might get through the use of a single wafer-scale swap.
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